NQSAP and 6502 Instructions
6502 Compatibility
The NQSAP has a 6502-inspired architecture and instruction set. The instructions and registers are similar, but the opcodes of the NQSAP do not map to the same values as a 6502. This means that the NQSAP and 6502 are somewhat compatible at the assembly language source level, but the object code they use is completely different.
The major difference in the two implementations is that the NQSAP is an 8-bit only machine with no 16-bit addressing modes. This means that the absolute addressing modes and the zero-page addressing modes are the same because all memory is in page zero. For simplicity of the documentation, the instructions are listed as using absolute, absolute+X, and absolute+Y modes instead of the zero-page modes.
Two other features of the 6502 are also not implemented: decimal mode and interrupts. This removes a few instructions from the complete set.
One interesting difference between the two implementations is the branch instructions. On the 6502, these use fewer cycles than an unconditional jump instruction because they only need to specify a single byte offset instead of a two byte absolute or relative address. On the NQSAP, the branch instructions are expensive because they need to save and restore one of the index registers in order to calculate relative addresses. A set of conditional jump instructions was added that mimics all of the conditional branches but uses absolute addressing instead of relative addressing. These jumps use only four cycles instead of the eight needed for a conditional branch.
Implementation Progress
Some of the single operand memory instructions, like INC, DEC, and ASL are not available for the indexed addressing modes because they require too many instruction cycles. These instructions need to save and restore the A register and that can’t be done in the eight cycles available. A register/flags redesign could fix this. Another possibility is to extend the maximum microinstruction cycles from eight to sixteen.
Instructions Common to 6502 and NQSAP
| Name | Description | Flags | Address Modes |
|---|---|---|---|
| ADC | Add with Carry | CZVN | IM,AB,AX,AY,IX,IY |
| AND | Logical AND | -Z-N | IM,AB,AX,AY,IX,IY |
| ASL1 | Arithmetic Shift Left | CZ-N | AA,AB,AX |
| BCC | Branch if Carry Clear | —- | RE |
| BCS | Branch if Carry Set | —- | RE |
| BEQ | Branch if Equal | —- | RE |
| BIT2 | Bit Test | -Z– | AB |
| BMI3 | Branch if Minus | —- | RE |
| BNE | Branch if Not Equal | —- | RE |
| BPL3 | Branch if Positive | —- | RE |
| BVC3 | Branch if Overflow Clear | —- | RE |
| BVS3 | Branch if Overflow Set | —- | RE |
| CLC3 | Clear Carry | C— | IP |
| CLV3 | Clear Overflow | –V- | IP |
| CMP4 | Compare A | CZ-N | IM,AB,AX,AY,IX,IY |
| CPX4 | Compare X | CZ-N | IM,AB |
| CPY4 | Compare Y | CZ-N | IM,AB |
| DEC | Decrement Memory | -Z-N | AB,AX |
| DEX | Decrement X | -Z-N | IP |
| DEY | Decrement Y | -Z-N | IP |
| EOR | Exclusive OR | -Z-N | IM,AB,AX,AY,IX,IY |
| INC | Increment Memory | -Z-N | AB,AX |
| INX | Increment X | -Z-N | IP |
| INY | Increment Y | -Z-N | IP |
| JMP | Jump | —- | AB,IN |
| JSR | Jump to Subroutine | —- | AB |
| LDA5 | Load A | -Z-N | IM,AB,AX,AY,IX,IY |
| LDX5 | Load X | -Z-N | IM,AB,AY |
| LDY5 | Load Y | -Z-N | IM,AB,AX |
| LSR6 | Logical Shift Right | CZ-N | AA,AB,AX |
| NOP | No Operation | —- | IP |
| ORA | Logical Inclusive OR | -Z-N | IM,AB,AX,AY,IX,IY |
| PHA | Push A | —- | IP |
| PHP | Push Processor Status | —- | IP |
| PLA5 | Pull A | -Z-N | IP |
| PLP | Pull Processor Status | CZVN | IP |
| ROL6 | Rotate Left | CZ-N | AA,AB,AX |
| ROR6 | Rotate Right | CZ-N | AA,AB,AX |
| RTS | Return from Subroutine | —- | IP |
| SBC | Subtract with Carry | CZVN | IM,AB,AX,AY,IX,IY |
| SEC | Set Carry | C— | IP |
| STA | Store A | —- | AB,AX,AY,IX,IY |
| STX | Store X | —- | AB,AY |
| STY | Store Y | —- | AB,AX |
| TAX5 | Transfer A to X | -Z-N | IP |
| TAY5 | Transfer A to Y | -Z-N | IP |
| TSX5 | Transfer SP to X | -Z-N | IP |
| TXA5 | Transfer X to A | -Z-N | IP |
| TXS | Transfer X to SP | —- | IP |
| TYA5 | Transfer Y to A | -Z-N | IP |
Notes:
- Does not set C flag. Will be fixed in flags redesign
- Does not set V and N flags
- Requires V and N flags and ability to update, set, and clear individual flags. Redesign in progress to replace flags register with D flip-flops
- Need to share ALU opcode with the SBC operation. Redesign in progress to override IR and force ALU into subtract mode
- Zero and Negative flags not yet set for non-ALU instructions
- Requires new A register hardware
6502 Instructions Not Implemented in NQSAP
| Name | Description | Flags | Address Modes |
|---|---|---|---|
| BRK1 | Force Interrupt | —- | |
| CLD2 | Clear Decimal Mode | —- | |
| CLI1 | Clear Interrupt Disable | —- | |
| RTI1 | Return from Interrupt | —- | |
| SED2 | Set Decimal Mode | —- | |
| SEI1 | Set interrupt Disable | —- |
Notes:
- No support for interrupts
- No support for decimal mode
NQSAP Extensions
| Name | Description | Flags | Address Modes |
|---|---|---|---|
| DEA | Decrement A | -Z-N | AA |
| INA | Increment A | -Z-N | AA |
| JCC | Jump if Carry Clear | —- | AB |
| JCS | Jump if Carry Set | —- | AB |
| JEQ | Jump if Equal | —- | AB |
| JMI | Jump if Minus | —- | AB |
| JNE | Jump if Not Equal | —- | AB |
| JPL | Jump if Positive | —- | AB |
| JVC | Jump if Overflow Clear | —- | AB |
| JVS | Jump if Overflow Set | —- | AB |
| NOT | Bitwise NOT A | -Z-N | AA |
| OUT | Output A | —- | IP |
this file was generated by nqsap-instructions.py at 25-Mar-2021 11:57:28