6502 Compatibility

The NQSAP has a 6502-inspired architecture and instruction set. The instructions and registers are similar, but the opcodes of the NQSAP do not map to the same values as a 6502. This means that the NQSAP and 6502 are somewhat compatible at the assembly language source level, but the object code they use is completely different.

The major difference in the two implementations is that the NQSAP is an 8-bit only machine with no 16-bit addressing modes. This means that the absolute addressing modes and the zero-page addressing modes are the same because all memory is in page zero. For simplicity of the documentation, the instructions are listed as using absolute, absolute+X, and absolute+Y modes instead of the zero-page modes.

Two other features of the 6502 are also not implemented: decimal mode and interrupts. This removes a few instructions from the complete set.

One interesting difference between the two implementations is the branch instructions. On the 6502, these use fewer cycles than an unconditional jump instruction because they only need to specify a single byte offset instead of a two byte absolute or relative address. On the NQSAP, the branch instructions are expensive because they need to save and restore one of the index registers in order to calculate relative addresses. A set of conditional jump instructions was added that mimics all of the conditional branches but uses absolute addressing instead of relative addressing. These jumps use only four cycles instead of the eight needed for a conditional branch.

Instructions Common to 6502 and NQSAP

Name Description Flags Address Modes
ADC Add with Carry CZVN IM,AB,AX,AY,IX,IY
AND Logical AND -Z-N IM,AB,AX,AY,IX,IY
ASL Arithmetic Shift Left CZ-N AA,AB,AX
BCC Branch if Carry Clear —- RE
BCS Branch if Carry Set —- RE
BEQ Branch if Equal —- RE
BIT Bit Test -Z– AB
BMI Branch if Minus —- RE
BNE Branch if Not Equal —- RE
BPL Branch if Positive —- RE
BVC Branch if Overflow Clear —- RE
BVS Branch if Overflow Set —- RE
CLC Clear Carry C— IP
CLV Clear Overflow –V- IP
CMP Compare A CZ-N IM,AB,AX,AY,IX,IY
CPX Compare X CZ-N IM,AB
CPY Compare Y CZ-N IM,AB
DEC Decrement Memory -Z-N AB,AX
DEX Decrement X -Z-N IP
DEY Decrement Y -Z-N IP
EOR Exclusive OR -Z-N IM,AB,AX,AY,IX,IY
INC Increment Memory -Z-N AB,AX
INX Increment X -Z-N IP
INY Increment Y -Z-N IP
JMP Jump —- AB,IN
JSR Jump to Subroutine —- AB
LDA Load A -Z-N IM,AB,AX,AY,IX,IY
LDX Load X -Z-N IM,AB,AY
LDY Load Y -Z-N IM,AB,AX
LSR Logical Shift Right CZ-N AA,AB,AX
NOP No Operation —- IP
ORA Logical Inclusive OR -Z-N IM,AB,AX,AY,IX,IY
PHA Push A —- IP
PHP Push Processor Status —- IP
PLA Pull A -Z-N IP
PLP Pull Processor Status CZVN IP
ROL Rotate Left CZ-N AA,AB,AX
ROR Rotate Right CZ-N AA,AB,AX
RTS Return from Subroutine —- IP
SBC Subtract with Carry CZVN IM,AB,AX,AY,IX,IY
SEC Set Carry C— IP
STA Store A —- AB,AX,AY,IX,IY
STX Store X —- AB,AY
STY Store Y —- AB,AX
TAX Transfer A to X -Z-N IP
TAY Transfer A to Y -Z-N IP
TSX Transfer SP to X -Z-N IP
TXA Transfer X to A -Z-N IP
TXS Transfer X to SP —- IP
TYA Transfer Y to A -Z-N IP

6502 Instructions Not Implemented in NQSAP

Name Description Flags Address Modes
BRK1 Force Interrupt —-  
CLD2 Clear Decimal Mode —-  
CLI1 Clear Interrupt Disable —-  
RTI1 Return from Interrupt —-  
SED2 Set Decimal Mode —-  
SEI1 Set interrupt Disable —-  

Notes:

  1. No support for interrupts
  2. No support for decimal mode

NQSAP Extensions

Name Description Flags Address Modes
DEA Decrement A -Z-N AA
INA Increment A -Z-N AA
JCC Jump if Carry Clear —- AB
JCS Jump if Carry Set —- AB
JEQ Jump if Equal —- AB
JMI Jump if Minus —- AB
JNE Jump if Not Equal —- AB
JPL Jump if Positive —- AB
JVC Jump if Overflow Clear —- AB
JVS Jump if Overflow Set —- AB
NOT Bitwise NOT A -Z-N AA
OUT Output A —- IP

this file was generated by nqsap-instructions.py at 17-Dec-2021 21:15:08

Updated: